Quartus II Verification and Optimization

VEC103: Quartus II Verification and Optimization

The class integrates two much correlated Altera's classes, Altera Verification traning and Altera Optimization traning.

In the Verification section You will learn features of the Quartus® II software that will enable you to verify your FPGA design*. You will learn how to simulate Altera IP and megafunctions in other EDA simulation tools and how to use NativeLink to simulate directly in the Quartus II software from 3rd-party tools. You will also estimate FPGA power consumption using tools found in the Quartus II software. You will use debugging tools available in the Quartus II software, such as the SignalTap® II embedded logic analyzer, In-System Sources & Probes, & the Logic Analyzer Interface. You will learn to select the correct tool to effectively debug your design. *Some (not all) features examined by this course apply to CPLD designs

In the Optimization section You will learn advanced features of the Quartus® II design software  that will enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock™ regions in the Quartus II software to reduce compile times and preserve performance on selected regions of your designs. You will obtain your design goals in the area of performance, resource usage and power consumption by using design strategies, HDL coding styles and Quartus II software settings. You will also learn how to manage compile times effectively.

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