VEC108: Interfacing to External Memory with FPGA
You will learn to implement external memory interfaces with Altera® FPGAs & Quartus® II software. The course provides lecture & lab exercises to help you understand the design flows, your options, & the challenges you will face. Since Double Data Rate (DDR) interfaces are most prevalent, we will focus on implementing DDR 2 & 3 memory interfaces. You will learn the memory interface options you have & how to implement a "High Performance" DDR SDRAM controller with auto-calibrating phy block. This type of memory controller exploits the ALTMEMPHY core to achieve the highest system bandwidth. You will also learn how to take advantage of the self-service resources available. This should improve your confidence that you can successfully complete a memory interfacing design.